The present invention relates to the field of integrated circuit correction, and more specifically, to the redundancy correction of read-only memory (ROM) circuits.
A ROM contains binary information which is written at its manufacturing, generally by using a coding mask specific to the data contained in the memory.
Several types of defects can appear in a ROM during its manufacturing. Some defects can make the memory completely inoperative, for example, an address decoding defect preventing a proper reading of the stored data. Other defects may concern a portion of the memory only, for example, when a cell provides in the read mode a value opposite to the expected value. This particular type of defect is considered hereafter.
A way of testing the proper manufacturing of a ROM consists of reading its content and checking that all the stored information is correct. This test operation is lengthy and expensive, and an embarked testing device is included in a ROM. Such a device is designed for, during a test phase, successively receiving all the data stored in the memory, adding them, multiplying them, etc. according to an adequate encryption algorithm, and comparing the final result with the result expected from the memory data. When the results are equal, the memory is assumed to be good.
ROMs are currently integrated in large digital circuits, to store information such as fonts in a display control circuit, or such as square roots in a tracking circuit or such as the microcode of an application. If a ROM of such a circuit is defective, the circuit is inoperative and is thrown away.
An advantage of an embodiment of the present invention is to provide a means of relatively simple implementation for repairing a possible manufacturing defect in a ROM.
An embodiment of the present invention provides a ROM including an array, each cell of which is accessible by a column address and a row address, including a parity memory for storing an expected parity of each row and of each column, an electrically programmable one-time programmable address memory, a testing circuit for, during a test phase, calculating a parity of each row and of each column, comparing calculated and expected parities for each row and each column, and in case the calculated and expected parities are not equal, marking the row or column in the address memory, and a correction circuit for, in normal mode, inverting a value read from the array cell having its row and column marked in the address memory.
According to an embodiment of the present invention, the address memory includes a marking column and a marking row respectively associated with the array rows and columns, the testing circuit marking a row by enabling a flag in the cell of same row of the marking column, and marking a column by enabling a flag in the cell of same column of the marking row.
According to an embodiment of the present invention, the address memory includes a column address memory in which the testing circuit marks a column by writing its column address and a row address memory in which the circuit marks a row by writing its row address.
According to an embodiment of the present invention, the ROM array is divided into several sub-arrays, each sub-array being associated with a parity memory and an address memory.
The foregoing features and advantages of embodiments of the present invention, will be discussed in detail in the following non-limiting and non-exhaustive description of specific embodiments in connection with the accompanying drawings.